i spent some time this evening looking over the schematic and datasheets from the design that Geoff Lyon at HP did. I've got a firm understanding of how the flashboard works now -- and it's quite straightforward and gives lots of hope for the future.
First, take a look at the schematic found at
(sorry for the hotlinking as I dont have available web space of my own ATM
):
http://www.handhelds.org/download/projects/jornada/720/j720_flash_card/memcard/Jornada720%20Memory/
Now, I'll walk folks through this.
1
) note that the Flash and SDRAM chips are separated into pairs 'A' and 'B'. Pair A is the A-set Flash and SDRAM chip. Pair B is the B-set Flash and SDRAM chip.
(so far, so good, so easy
)
2
) Note the address lines marked as A0..A24 . This is a 25-bit address line is masked to ALL FOUR memory IC's. That is, whenever the address lines are asserted, all four chips 'see' the address being request. However, note that only the Flash chips use all 25-bits of the address. The various ICs are 'separated' via Write-Enable and Read-Enable lines that allow a chip to only react when it is properly 'called upon'. The SDRAM memory IC's use a 12-bit addressing scheme and these 12 bits come from the upper 12 bits of the 25-bit address bus
(this is important in a few steps
).
3
)Next, note that the data lines, marked Dx0..Dx15
(where x can be 'A' or 'B'
. This is important because it splits the data lines into a 16-bit 'A' set of data and a 16-bit 'B' set of data. Each IC can only support a 16-bit data bus so two ICs
(either two SDRAM or two Flash
) are used in tandem at the same time to create a 32-bit wide data bus. This is _exactly_ the same concept as RAID striping in hard disks.
4
) So.... when the J720 first boots, it immediately begins reading 32-bit instructions from address 0x000000h
(which corresponds to address lines 0-24 on the Flash IC
). The code it executes at this time will be things like the bootloader and CPU initialization. Eventually it will run enough code that it'll be started and running and it will then use the upper 12 bits of the address bus to store user data in memory since the operating system fits well within the low-order 13 bits
(~8MB
) of the address range.
(at this point you may be asking 'if the flash chip doesnt _need_ all 24 bit of the address range to run then why are they used?' -- the answer to this has to do with the differences in SDRAM and Flash technologies and is beyond the scope of this brief discussion
).
5
) Here's where this helps us with running Linux. So, in order to 'flash in place' for the new versions of the bootloader or a new Linux OS, here's what needs to happen. Use a bootloader that has a small overhead
(such that it can all be loaded into memory
). Boot like normal and then drop into the 'administrative console' running _entirely_ in user memory
(the upper 12-bits
). This leaves the address lines and the data lines for the Flash chips completely usable. Then allow the user to connect via USB or Modem or RS232
(U-Boot supports this
) and re-program the Flash chips while they are installed in the J720 because the address/data lines for the Flash chips are not being used at that moment.
It's late here in Las Vegas and I couldn't sleep because the ideas were running through my head and I wanted to share them with the group. If I've omitted any details or anything is unclear because of my late-night zeal, then let me know and I'll clarify.
This should _drastically_ help out once a user has a Linux-based J720 up and running. However, it still does not solve the problem of the initial programming of the flash chips.
while slow, it should be entirely possible to implement a flashing board using the male molex connector, a PIC-Micro, and a RS232 transceiver. The code is straight-forward -- receiver the data serially and then mux it out to the molex connector inside the PIC-Micro. Again, slow due to the size of the Flash ROM but better than nothing.
