tenjeangosi> You seemed to have the right development tools - aren't they all related to the Philips Poseidon family?
-Compaq 2010c
-Velo 1
-Nino 320
Thanks
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The two most popular CPUs seem to be the NEC VR41xx family, used in the Casio Cassiopeia and Everex Freestyle
(and others
), and the Philips PR31700, used in the Philips Nino
(and others
). The Toshiba R39xx family is also used in some WinCE devices, but these chips are apparently very similar, if not equivelant to members of the Philips Poseidon family of CPUs, such as PR31700. There are probably WinCE devices based on other families of MIPS CPUs as well.
Although each of these families is based on a MIPS CPU core, they define their peripheral registers differently. Because of this, the MIPS portion of Linux CE is further divided into separate platforms, one for each CPU family. Devices that share the same CPU family, such as the Cassiopeia and Freestyle, can use most of the same platform-specific code because almost everything is built into the CPU and 1 or 2 support chips, but there are device-specifics that also need to be addressed.
The Philips Poseidon parts are based on a MIPS R3000 core, while the NEC VR41xx parts are R4000 core with some parts missing. The exception handling code and the TLB-related code are R4000-style, but like an R3000 it lacks the LL/SC instruction pair used to do atomic accesses in the MIPS kernel. In some cases, VR41xx is like neither R3000 nor R4000, for example the ability to handle a 1K page size. Both Poseidon and VR41xx lack floating point coprocessors.
http://www.hacksrus.com/~mike/lince/lince-mips.htm
http://members.fortunecity.com/celinux1/faq1.html
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Poseidon
From LinuxMIPS
PR31100
PR31100 is is a single-chip, low-cost, integrated embedded processor. PR31100 consists of a 40MHz R3000 3.3V static CMOS CPU with 4 K Instruction / 1 K Data cache memory, w/o MMU, multiple DMA channels and a high-performance and flexible Bus Interface Unit
(BIU
) and external I/O modules.
PR31500
Poseidon v1.0
PR31500 is a 37MHz R3000 3.3V static CMOS CPU with R3000A TLB and 4K Instrution / 1K Data cache. PR31500 also contains multi-channel DMA controller, ROM, Flash, RAM, DRAM, SDRAM, SRAM, and PCMCIA controller and Dual-UART, SPI and High-speed serial interface controllers. Philips licensed a version of Toshiba's R3900 MIPS RISC processor core for the PR31500.
TwoChipPIC
(for Personal Intelligent Communicator
) chipset consists of the PR31500 microcontroller and the UCB1100 analog interface chip. The UCB1100
(http://www.semiconductors.philips.com/pip/UCB1100_2.html
) provides a 12-bit audio codec and a 14-bit modem codec, a touchscreen interface, and a 10-bit A/D converter for measuring battery voltages and other analog inputs.
PR31700
Poseidon v1.5
The PR31700 is a 75MHz R3000
(PR3901 Processor Core
) with MMU, 4K Instruction / 1K Data cache. PR31700 also contains multi-channel DMA controller, ROM, Flash, RAM, DRAM, SDRAM, SRAM, and PCMCIA controller. It is also identical to the Toshiba 3912 processor from the TX39XX family. It is pretty clear that Philips licensed or bought this core directly from Toshiba.
The TwoChipPIC Plus chipset consists of Philips’ PR31700 and UCB1200 analog chip.
I think that the datasheets are linked from that French
(Paul's
) site
http://www.linux-mips.org/wiki/Poseidon
I have wanted one anyway, and if it has Linux+++++
